![]() Since a flip-flop in the receiving clock domain can sample a signal from the driving domain at any point in time, even a very narrow glitch might be captured and treated as a valid value. The third common error in multi-clock design is allowing glitch propagation from the driving clock domain to the receiving clock domain. Problem #3: Glitch elimination across clock domain boundariesĪlthough synchronization eliminates meta-stability for all practical purposes, it is not sufficient to fix other types of multi-clock design errors. This can be accomplished by having a separate synchronizer for the reset signal as it enters into each clock domain in the design. However, when reset is deactivated it must be properly synchronized so that flip-flops do not become meta-stable as they come out of the reset state. There is no need for synchronization on the activation edge of reset, since by definition all state elements are reset to initial values, and the reset signal will generally be held active for enough cycles to allow any meta-stability to settle out. Generally, the entire SoC can be reset by a single signal, which therefore must propagate to all clocked elements in all clock domains. Designers sometimes forget that reset signals are subject to meta-stability and must be protected by synchronizers. Improper synchronization of reset signals is a related problem in multi-clock designs. The double-level flip-flop structure is often called a synchronizer, and designers commonly speak of synchronizing signals across clock domains. Even if the first flip-flop does become meta-stable, there is an extremely high likelihood that the signal will settle by the time that it passes through the second level. Most designers also know that the textbook solution to meta-stability is using two levels of flip-flops on each signal crossing a clock domain boundary. These effects typically include loss of critical handshake signals between clocks domains, and corruption of multi-bit data"serious problems that are highly likely to require a chip re-spin. GHz-rate chips with clocking design errors can exhibit the effects of meta-stability quite quickly when running in real systems. This is not just a theoretical potential. Whenever this happens, there is a possibility of meta-stability in the receiving clock domain. Because there is no defined temporal relationship between the clock and the signal, it is entirely possible that they could transition at the same time. On a truly asynchronous clock boundary, the receiving domain's clock is used to capture each signal from the driving domain in a flip-flop. It is critical that the output signal from the flip-flop not be used until it has settled. When this happens, the flip-flop may not immediately settle to a known value. ![]() Whenever a signal enters a clocked circuit element, such as a flip-flop, too close to the clock, there is the potential for meta-stability. Most designers understand that meta-stability is a real problem in real circuits the modern abstractions of RTL design and static timing analysis can't entirely shield designers from having to worry about the underlying physics. The first multi-clock problem that designers must consider is that of meta-stability as signals pass from one clock domain to another. The proper handing of signals across clock domain boundaries is critical for successful SoC design. The interface between logic on different clocks is called a clock domain crossing or clock domain boundary. Each such portion is known as a clock domain. There is also a trend toward designing major sub-blocks of SoCs to run on independent clocks to ease the problem of clock skew across large chips.įor all of these reasons, designers working on SoC projects are virtually certain to encounter multiple clocks and to be faced with the design of logic interconnecting two portions of the chip running on independent clocks. Many modern serial interfaces are inherently asynchronous from the rest of the chip some actually derive their clocks directly from the incoming data streams. Most SoC devices have multiple interfaces, some following standards that use very different clock frequencies. Multiple, independent clocks are ubiquitous in system-on-chip (SoC) design.
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